Ревізії fifo.v

1 file changed, 63 insertions

fifo.v(файл створено)

		@@ -0,0 +1,63 @@
1	+	module FIFO
2	+	#(
3	+	parameter NUMSAMPLES = 16,
4	+	parameter NUMBITS = 16
5	+	) (
6	+	input wire rclk,
7	+	input wire wclk,
8	+	input wire reset,
9	+	input wire [NUMBITS-1:0] wdata,
10	+	input wire readEnable,
11	+	input wire writeEnable,
12	+	output [NUMBITS-1:0] rdata,
13	+	output wire isEmpty,
14	+	output wire isFull
15	+	);
16	+	localparam ABITS = $clog2(NUMSAMPLES); // Minimum required address bits
17	+
18	+	reg [NUMBITS-1:0] rdata;
19	+	reg [NUMBITS-1:0] fifo [0:NUMSAMPLES];
20	+	wire [ABITS:0] writePtr;
21	+	wire [ABITS:0] readPtr;
22	+
23	+	GrayCounter #(
24	+	.BITS(ABITS+1)
25	+	) writeCounter (
26	+	wclk,
27	+	reset,
28	+	writeEnable,
29	+	writePtr
30	+	);
31	+
32	+	wire fullOrEmpty = (writePtr[ABITS-1:0] == readPtr[ABITS-1:0]);
33	+	wire empty = (writePtr == readPtr);
34	+	wire [ABITS-1:0] wAddr = writePtr[ABITS-1:0];
35	+	wire [ABITS-1:0] rAddr = readPtr[ABITS-1:0];
36	+
37	+	GrayCounter #(
38	+	.BITS(ABITS+1)
39	+	) readCounter (
40	+	.clk(rclk),
41	+	.reset(reset),
42	+	.enable(readEnable && !empty),
43	+	.out(readPtr)
44	+	);
45	+
46	+
47	+	assign isEmpty = empty;
48	+	assign isFull = fullOrEmpty && !empty;
49	+
50	+	always @(posedge rclk)
51	+	begin
52	+	if (readEnable)
53	+	rdata <= reset ? 0 : fifo[rAddr];
54	+	else
55	+	rdata <= 0;
56	+	end
57	+
58	+	always @(posedge wclk)
59	+	begin
60	+	if (!reset && writeEnable) fifo[wAddr] <= wdata;
61	+	end
62	+
63	+	endmodule

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